Subject: Re: [linux-audio-dev] changing control port values with LADSPA: a serious issue?
From: David Olofson (david_AT_gardena.net)
Date: Mon Mar 18 2002 - 08:13:41 EET
On Sunday 17 March 2002 07.24, Bob Colwell wrote:
> >> Does this not apply to the instruction cache as well--
> >
> >Yes. In fact, most modern CPUs don't even have a separate
> > instruction cache. (The 68k CPUs up to 030 did, though - not sure
> > about the rest.)
>
> The P6 family has separate I and D L1 caches. The Pentium 4 has a
> trace cache, which stores entire sequences of decoded micro-ops,
> thus (by implication) storing any embedded branch predictions as
> well. The Level 2 and higher caches are unified, combining data
> and instructions.
Ok, thanks for the detailed info.
> >Of course, with a decent FPU, you could just run all of that in
> > your inner loop and get away with it - but you can forget about
> > real time on a Pentium! (A Pentium *would* handle the actual
> > filter without complaining too much, though.)
>
> Do you really mean a Pentium, or do you mean a Pentium II, III, or
> 4? And if you mean anything other than a Pentium, why did you say
> that?
Pentium and Pentium MMX - the newer ones should have sufficiently
fast trig in their FPUs, AFAIK.
//David
.- M A I A -------------------------------------------------.
| Multimedia Application Integration Architecture |
| A Free/Open Source Plugin API for Professional Multimedia |
`----------------------> http://www.linuxaudiodev.com/maia -'
.- David Olofson -------------------------------------------.
| Audio Hacker - Open Source Advocate - Singer - Songwriter |
`-------------------------------------> http://olofson.net -'
This archive was generated by hypermail 2b28 : Mon Mar 18 2002 - 08:03:57 EET