On Oct 20, 2008, at 3:18 PM, Olivier Guilyardi wrote:
> What about the test-int-array-* family of tests on PPC?
They all pass on my uniprocessor G4, but that doesn't
really tell us much. Anybody got a multiprocessor PPC?
This stuff makes my head hurt, too, but as best I can
figure out, I believe the jack code needs memory
barriers on several non-x86 architectures with weak
memory ordering, PPC probably being the most
common. It appears to me that without barriers,
there's a small chance reordered writes on one
processor could result in another processor reading
invalid data:
CPU1: CPU2:
write index ---
write data2 read index
write data3 read data1 <- invalid
write data1 read data2
--- read data3
x
Paul E. McKenney
Memory Ordering in Modern Microprocessors, Part I
http://www.linuxjournal.com/article/8211
Memory Ordering in Modern Microprocessors, Part II
http://www.linuxjournal.com/article/8212
Linus Torvalds
Re: Memory barriers and spin_unlock safety
http://lkml.org/lkml/2006/3/3/142
Parts of this *thread*
Re: Re: [liblf-dev] Possible lock-free ring buffer: msg#00152
http://techweb.rfa.org/pipermail/portaudio/2006-May/005661.html
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Received on Thu Oct 23 00:15:01 2008
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