On Mon, 2009-05-11 at 17:54 +0200, Jens M Andreasen wrote:
> If it indeed is SSE that gives the performance advantage rather than the
> caheline, then the rules can be relaxed from powers of 2 to multiples of
> 4 (floats).
Make that multiples of 16, and the buffer will be aligned with the
caheline as well (for P4 - Core2.) So buffersizes of 48, 96 and why not
192 should be quite OK.
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Received on Mon May 11 20:15:04 2009
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