Subject: Re: [linux-audio-dev] optimization / restrictions
From: Yann Orlarey (orlarey_AT_grame.fr)
Date: Fri May 18 2001 - 11:00:37 EEST
When you use multiple buffers at the same time, you must take care of
address aliasing problems, that is different addresses that compete for the
same n-ways group of cache lines. For example for the Pentium 4 you must
try to avoid using simultaneously addresses modulo 2K for the level 1 data
cache, 32K for the level 2 data cache. This is explained in the "Intel
Pentium 4 Processor Optimization Reference Manual" p 2-35.
At 5:25 PM +0200 17/05/01, n++k wrote:
>[Steve Harris <S.W.Harris_AT_ecs.soton.ac.uk>]
>|
>| Known nominal 0db value (e.g. 1.0f)
>| Minimum sample rate (e.g. 44.1k's)
>| Guaranteed 2^n block size
>
>Somewhere (in a diskmag) I read Tammo Hinrichs (writing about
>his softsynth system)
>
>"A bad idea, however, is to make your buffer sizes a power of two.
>The times when ASM coders used AND operations to mask out the buffer
>offsets
>are over. Those one or two cycles for a compare operation don't
>hurt. So, there's no reason for using power-of-two bffer sizes
>except you may be used to it. And in fact, it's even better if
>you don't. I won't go into too much detail here, but if you know
>how a cache tag RAM works, you might realize that the CPU can
>manage the cache better if the buffers start at "weird" addresses,
>especially if you use multiple buffers at a time (eg. in the
>same loop). Just make the buffer adderesses a multiple of 32,
>don't make their sizes a power of two (or leave some space
>between the buffers, even one dword is enough) and you're set."
>
>I personally wondered what he meant here about the cache operation
>of the CPU, anybody knows more about that and/or care to comment?
>
>--
> n
>++k
-Yo-
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Yann Orlarey, (orlarey_AT_grame.fr)
GRAME, 9 rue du Garet, BP 1185, 69202 Lyon, France
http://www.grame.fr
telephone : +33 (0)4 72 07 37 00, fax : +33 (0)4 72 07 37 01
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