>On Fri, 2005-04-15 at 18:18 +0200, Wolfgang Woehl wrote:
>> Paul Davis <paul@email-addr-hidden>:
>> > >What are the constraints for the HDSP 9652's apparent minimum buffer
>> > >size of 64 frames? Is it the FPGA? Is it the firmware?
>> >
>> > whatever stuff is programmed into the FPGA and/or the rest of the
>> > board, it cannot be set to generate interrupts at smaller intervals
>> > than this.
>>
>> Paul, would you think it's worth trying to find out deeper detail on
>> this? Me thinking if the 9652 can do 96khz/64 frames (1.33 msecs) it
>> can actually go quicker than the 44.1khz/64 frames (2.9 msecs) setup.
>> Is there any potential or would one only waste time?
>>
>
>Well, what happens if you just change the driver to allow 44.1/32? It's
>probably one or two lines of code.
you guys are not understanding me. when you set the buffer size, you
are setting a register value in the HDSP. the h/w doesn't understand
any values lower than 64. in fact, it not only doesn't understand, it
has no way to even request it.
--p
Received on Sat Apr 16 00:15:05 2005
This archive was generated by hypermail 2.1.8 : Sat Apr 16 2005 - 00:15:05 EEST