On Fri, 2005-04-15 at 18:18 +0200, Wolfgang Woehl wrote:
> Paul Davis <paul@email-addr-hidden>:
> > >What are the constraints for the HDSP 9652's apparent minimum buffer
> > >size of 64 frames? Is it the FPGA? Is it the firmware?
> >
> > whatever stuff is programmed into the FPGA and/or the rest of the
> > board, it cannot be set to generate interrupts at smaller intervals
> > than this.
>
> Paul, would you think it's worth trying to find out deeper detail on
> this? Me thinking if the 9652 can do 96khz/64 frames (1.33 msecs) it
> can actually go quicker than the 44.1khz/64 frames (2.9 msecs) setup.
> Is there any potential or would one only waste time?
>
Well, what happens if you just change the driver to allow 44.1/32? It's
probably one or two lines of code.
Lee
Received on Fri Apr 15 20:15:11 2005
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