On Wed, Apr 05, 2006 at 07:52:26PM -0500, Richard Smith wrote:
> Getting that to fly in an FPGA however may be the problem as you start
> running into clock speed limits. And an ASIC suffers from the lack of
> startup cash.
I've seen a 64 channel interface fit into a single Spartan 2E that was
small enough to be supported free Xilinx Webpack. Since then, the
current web pack supports spartan3s that are bigger and faster than that
project used.
-- Joshua D. Boyd jdboyd@email-addr-hidden http://www.jdboyd.net/ http://www.joshuaboyd.org/Received on Fri Apr 7 00:15:16 2006
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