Re: [LAD] media clock from wall clock

On Sun, Oct 12, 2014 at 02:42:19PM -0700, Len Ovens wrote:
> On Sun, 12 Oct 2014, Fons Adriaensen wrote:
>
> >On Sun, Oct 12, 2014 at 08:50:31AM -0700, Len Ovens wrote:
> >
> >>The first thing I find is that it is not possible to get even word
> >>clock via simple math. The wall clock moves one tick per usec which
> >>at 48K is 20.833rep. (44.1k is a mess) I would suggest this is why
> >>AVB and AES67 at lowest latency already uses 6 sample frames which
> >>is a nice even 125 usec.
> >
> >This is a non-problem. A PLL/DLL (which is what any system that
> >syncs one clock to another will amount to) can be made for any
> >ratio of integers.
>
> In HW it is a non-problem. I am not so sure that is true in SW on a
> machine that is also running a DE, and a DAW on top of that. That
> is, I think that a cpu that has nothing to do but make a media clock
> would have no problem doing this.

What I meant is that it doesn't depend on having 'nice even' numbers.

Controlling a HW oscillator that generates a sample clock synced to
a system clock is exactly the same problem as finding out the correct
resample ratio given two clocks, as done by njbridge. The requirements
are that the HW oscillator frequency can be controlled in small steps
and that it has very low phase noise in the audio range, i.e. it must
be a jitter-free sample clock on its own.

The very low loop BW ensures that any jitter on the system clock,
including that caused by scheduling latencies etc. on a busy system,
is filtered out.

Ciao,

-- 
FA
A world of exhaustive, reliable metadata would be an utopia.
It's also a pipe-dream, founded on self-delusion, nerd hubris
and hysterically inflated market opportunities. (Cory Doctorow)
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